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NXP Launches First S32 Automotive Processors

Eight months after announcing its "whole vehicle" automotive processing platform last October, NXP used its annual NXP Connects conference here last week to announce a new family of processors to manage the systems that accelerate, brake and steer vehicles safely, whether under the direct control of a driver or an autonomous vehicle’s control.

The new 16nm 800MHz NXP S32S microcontrollers meet the needs of carmakers developing future autonomous and hybrid electric vehicles, and the company claims to offer the highest performance ASIL D capability available today.

The key focus is on safely and securely acting in autonomous environments, which is why the company decided to use the new Arm Cortex-R52 cores, according to Ray Cornyn, responsible for vehicle dynamics and safety products at NXP.

“When we started the development of the S32S it was clear that just building another incremental microcontroller was not what customers needed to handle the safety and performance requirements of next-generation and autonomous vehicles," Cornyn said. "Our new safety processors leverage the high performance multi-core benefits of the S32 Arm platform while still supporting traditional microcontroller ease of use and environmental robustness.”

Cornyn added that security upgradability over the air was also one of the reasons the company waited for the Arm core availability to launch the S32S.

Cars are evolving from taking simple instructions from a human driver to an increasingly sophisticated computing platform that senses, thinks and acts autonomously, according to NXP. While vehicle control systems traditionally responded directly to a driver’s commands, in autonomous systems, it is the car that gives those commands and then must execute them flawlessly to guarantee safety in all conditions. This need for safe guaranteed control has driven a rapid growth in demand for high-performance, safe computing solutions to control the “start, stop and steer” functions fundamental to all mobility.

"We see that the shift to next-generation autonomous and electric vehicles is introducing huge challenges to carmakers," said Ian Riches, executive director in Strategy Analytics’ global automotive practice. "Not least of these is the ability to get silicon in hand fast enough and with enough performance headroom to ease the transitions to autonomous and advanced HEV/EV. A car can be extremely intelligent, but if it can’t act safely on a decision, you don’t have a reliable autonomous system at all.”

One of the features of the new processor is the four parallel "lockstep" pairs of processors, which Cornyn says provides a high-level of redundancy and safety. “Traditional microcontrollers typically have only two or three,” he said.

The array offers four fully independent ASIL D capable processing paths to support parallel safe computing. In addition, the S32S architecture supports a new "fail availability" capability allowing the device to continue to operate after detecting and isolating a failure – a critical capability for future autonomous applications.

Other features of the S32S include a large integrated flash memory (up to 64M bytes) supporting on-the-fly, over-the-air update capability with zero processor downtime; user programmable hardware security engine with private and public key support; available PCIe for ADAS domain supervisory applications; and advanced electric motor control peripherals with included motor control software libraries.

NXP has partnered with OpenSynergy to develop a fully featured, real-time hypervisor supporting the NXP S32S products. The COQOS Micro SDK is one of the first hypervisor platforms that takes advantage of the Arm Cortex-R52’s special hardware features, enabling the integration of multiple real-time operating systems onto microcontrollers requiring high levels of safety (up to ISO26262 ASIL D). Multiple vendor independent OS/stacks can also run on a single microcontroller.

The S32S will be sampling in Q4 2018 to NXP’s automotive alpha customers.